发明名称 Data check circuit
摘要 <p>A data check circuit comprising: a request signal output circuit configured to output a request signal for requesting occupation of a bus to an arbitration circuit configured to arbitrate the occupation of the bus, when a CPU connected, as a bus master, with the bus for accessing a memory outputs an instruction signal for providing an instruction for starting detection of whether or not data stored in the memory is correct; a data acquisition circuit configured to acquire data stored in the memory through the bus, when the arbitration circuit outputs a permission signal for permitting the occupation of the bus based on the request signal; and a data processing circuit configured to perform processing for detecting whether or not the acquired data is correct, the acquired data acquired by the data acquisition circuit.</p>
申请公布号 EP2261810(B1) 申请公布日期 2013.09.25
申请号 EP20100164519 申请日期 2010.05.31
申请人 SANYO ELECTRIC CO., LTD.;SANYO SEMICONDUCTOR CO., LTD. 发明人 OGINO, NAOYUKI
分类号 G06F13/38;G06F11/10 主分类号 G06F13/38
代理机构 代理人
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