Double edge triggered flip flop

摘要

A dual edge triggered flip flop circuit uses clock signals that are delayed from a first clock signal and from one another by respective intervals. A first set of the plurality of clock signals are used to operate a first latch circuit to allow first data to be conducted to a storage element for a period of time after a rising edge of a first clock signal. The clock signals are further used to operate a second latch circuit to allow second data to be conducted to the storage element for a period of time after a falling edge of the first clock signal.