发明名称 Pad-less gate-all around semiconductor nanowire FETs on bulk semiconductor wafers
摘要 A non-planar semiconductor device is provided including at least one semiconductor nanowire suspended above a semiconductor oxide layer present within a portion of a bulk semiconductor substrate. The semiconductor oxide layer has a topmost surface that is coplanar with a topmost surface of the bulk semiconductor substrate. A gate surrounds a portion of the at least one suspended semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate. The source region is in direct contact with an exposed end portion of the at least one suspended semiconductor nanowire, and the drain region is in direct contact with another exposed end portion of the at least one suspended semiconductor nanowire. The source and drain regions have an epitaxial relationship with the exposed end portions of the suspended semiconductor nanowire.
申请公布号 US8541295(B2) 申请公布日期 2013.09.24
申请号 US201313759641 申请日期 2013.02.05
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 SLEIGHT JEFFREY W.;CHANG JOSEPHINE B.;LAURER ISAAC;NARASIMHA SHREESH
分类号 H01L21/66 主分类号 H01L21/66
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