发明名称 |
Transactional memory preemption mechanism |
摘要 |
Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.
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申请公布号 |
US8544022(B2) |
申请公布日期 |
2013.09.24 |
申请号 |
US201213465115 |
申请日期 |
2012.05.07 |
申请人 |
ARNDT RICHARD L.;CAIN, III HAROLD W.;FREY BRADLY G.;MAY CATHY;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ARNDT RICHARD L.;CAIN, III HAROLD W.;FREY BRADLY G.;MAY CATHY |
分类号 |
G06F9/46;G06F11/00;G06F13/24;G06F15/00 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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