<p>An image correction processing device is provided in which an FPGA (15) comprises: a plurality of line buffers (17) that sequentially read the pixel data of scan lines from an imaging element (11) and temporarily store the pixel data for a plurality of lines; and a pixel data correction processing unit (18). The pixel data correction processing unit (18): designates a line (n) as a correction target, said line (n) being in the middle of the pixel data for the plurality of lines stored in the plurality of line buffers (17); uses the pixel data for the lines that are adjacent to the correction target line (n) to correct the pixel data for the correction target line (n); and transfers the post-correction pixel data to an image processing circuit (16). This type of processing is performed repeatedly by shifting the scan lines one by one so that the pixel data for each line of a frame from the imaging element (11) is corrected and sent sequentially to the image processing circuit (16).</p>
