Methods and Apparatus for Designing and Constructing Multi-port Memory Circuits with Voltage Assist

摘要

To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical "0" or logical "1" into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.