| 摘要 |
<p>A gate drive circuit and a display. The gate drive circuit comprises a plurality of cascaded shift registers. Each of the shift registers comprises a signal output circuit (32), a signal input circuit (31), a reverse circuit (33) and a logic circuit (33). The signal output circuit (32) receives a positive clock signal which comes from an external circuit, and the signal output circuit (32) comprises a clock transistor and a level transistor. When the clock transistor is conducting, the signal output circuit outputs a positive clock signal; and when the level transistor is conducting, the signal output circuit outputs a constant low-level signal. The signal input circuit (31) receives an output signal from a prior shift register, and enables the clock transistor to conduct when the output signal received from the prior shift register is effective. The reverse circuit (33) receives a reverse clock signal which comes from the external circuit. When the reverse clock signal is effective, the clock transistor is cut off, and the level transistor is made to conduct at the same time. The logic circuit (33) enables the clock transistor to maintain conduction before the level transistor is conducting. The gate drive circuit has low power consumption, a strong anti-interference capability and a stable output waveform.</p> |
