| 摘要 |
<p>An AD conversion circuit (10) is provided with: a clock generation circuit (150) that generates clock signals (211 and 212) including a first initial period (T2) that is either a high period or a low period and is the first period after reset cancellation, and including a plurality of normal periods (T3) that are positioned after the first initial period (T2) and are high periods or low periods that are shorter than the first initial period (T2); and an incremental AD converter (100) that operates using the clock signals (211 and 212).</p> |
