发明名称 Exception detection and thread rescheduling in a multi-core, multi-thread network processor
摘要 Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor.
申请公布号 US8537832(B2) 申请公布日期 2013.09.17
申请号 US201113046726 申请日期 2011.03.12
申请人 PIROG JERRY;MITAL DEEPAK;BURROUGHS WILLIAM;LSI CORPORATION 发明人 PIROG JERRY;MITAL DEEPAK;BURROUGHS WILLIAM
分类号 H04L12/28 主分类号 H04L12/28
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