发明名称 |
Macro layout verification appartus |
摘要 |
A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.
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申请公布号 |
US8539412(B2) |
申请公布日期 |
2013.09.17 |
申请号 |
US201213618553 |
申请日期 |
2012.09.14 |
申请人 |
ARAYAMA MASASHI;MAKINO SUMIKO;FUJITSU LIMITED |
发明人 |
ARAYAMA MASASHI;MAKINO SUMIKO |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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