发明名称 |
Method and apparatus for low power semiconductor chip layout and low power semiconductor chip |
摘要 |
A layout system is described comprising a layout unit configured to layout cells in a mask design for a semiconductor chip based on library cells for a specified process node; a non-critical path determination unit configured to determine a non-critical path in the semiconductor chip; a cell determination unit configured to determine a group of cells in the mask design that form a part of the non-critical path and determine the corresponding library cell for at least one of the group of cells; a library cell modifying unit configured to modify one or more corresponding library cells to form a corresponding modified library cell; and a cell replacement unit configured to replace a library cell in the group of cells in the mask design that form a part of the non-critical path with the corresponding modified library cell.
|
申请公布号 |
US8539388(B2) |
申请公布日期 |
2013.09.17 |
申请号 |
US20100852664 |
申请日期 |
2010.08.09 |
申请人 |
JOU CHEWN-PU;LIN MING-TSUN;HSUEH FU-LUNG;JUANG SHAUH-TEH;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
JOU CHEWN-PU;LIN MING-TSUN;HSUEH FU-LUNG;JUANG SHAUH-TEH |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|