Bit-synchronous feedback control of receiver sensitivity

摘要

A receiver including an amplifying section for converting a relatively low power digital input signal into a relatively high power digital output signal is configured to utilize an adjustable feedback signal that is synchronous with the bit rate of the incoming digital signal so as to modify the level of the feedback signal as a function of time along the width of each bit of the digital input signal, increasing the bandwidth of the receiver at the leading edge of each incoming bit and decreasing the bandwidth otherwise.