Arrays Of Vertically-Oriented Transistors, Memory Arrays Including Vertically-Oriented Transistors, And Memory Cells

摘要

An array includes a plurality of vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include an inner data/sense line elevationally inward of the access lines and which interconnect transistors in that column. An outer data/sense line is elevationally outward of the access lines and electrically couples to the inner data/sense line. Other embodiments are disclosed, including memory arrays and memory cells.