| 摘要 |
A circuit that supplies a clock signal to a load having a clock input section capable of suppressing power consumption is disclosed. A clock generating section generates a clock signal having an amplitude corresponding to an absolute value of an electric potential difference between a lower limit of a high-level input voltage VIH and an upper limit of a low-level input voltage VIL in a load having a clock input section; a level shift section shifts an electric potential while maintaining the amplitude of the clock signal so that a high-level electric potential of the clock signal is not less than the lower limit of the high-level input voltage VIH and a low-level electric potential of the clock signal does not exceed the upper limit of the low-level input voltage VIL, and a clock signal whose electric potential is shifted is supplied to the clock input section.
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