Single-poly floating-gate memory device

摘要

An erasable programmable single-poly nonvolatile memory cell includes a floating-gate transistor having a floating gate (36), a gate oxide layer (362) under the floating gate, and a channel region; and an erase gate region (35), wherein the floating gate (36) is extended to and is adjacent to the erase gate region (35). The gate oxide layer (362) comprises a first portion (362a) above the channel region of the floating-gate transistor and a second portion (362b)above the erase gate region, and a thickness of the first portion (362a) of the gate oxide layer is different from a thickness of the second portion (362b) of the gate oxide layer. The memory cell also comprises a select transistor in series with the floating-gate transistor.