发明名称 |
METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULES |
摘要 |
A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time. |
申请公布号 |
EP2460083(A4) |
申请公布日期 |
2013.09.11 |
申请号 |
EP20100806800 |
申请日期 |
2010.07.01 |
申请人 |
RAMBUS INC. |
发明人 |
VAIDYANATH, ARUN;HAMPEL, CRAIG E. |
分类号 |
G06F13/14;G06F12/00;G06F13/16 |
主分类号 |
G06F13/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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