发明名称 |
Method of large-area circuit layout recognition |
摘要 |
Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.
|
申请公布号 |
US8530337(B1) |
申请公布日期 |
2013.09.10 |
申请号 |
US201213530605 |
申请日期 |
2012.06.22 |
申请人 |
BEDELL STEPHEN W.;HEKMATSHOARTABARI BAHMAN;KHAKIFIROOZ ALI;OTT JOHN A.;SHAHIDI GHAVAM G.;SHAHRJERDI DAVOOD;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BEDELL STEPHEN W.;HEKMATSHOARTABARI BAHMAN;KHAKIFIROOZ ALI;OTT JOHN A.;SHAHIDI GHAVAM G.;SHAHRJERDI DAVOOD |
分类号 |
H01L21/304 |
主分类号 |
H01L21/304 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|