发明名称 |
Multiple-grid exposure method |
摘要 |
A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (Deltat) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.
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申请公布号 |
US8530121(B2) |
申请公布日期 |
2013.09.10 |
申请号 |
US201213368877 |
申请日期 |
2012.02.08 |
申请人 |
WANG WEN CHUAN;LIN SHY-JAY;LIU PEI-YI;SHIN JAW-JUNG;LIN BURN JENG;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
WANG WEN CHUAN;LIN SHY-JAY;LIU PEI-YI;SHIN JAW-JUNG;LIN BURN JENG |
分类号 |
G03F9/00;G03G5/00 |
主分类号 |
G03F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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