发明名称 |
Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design |
摘要 |
In order to realize some of the advantages described above, there is provided a computer-implemented method for verification of an intellectual property (IP) core in a system-on-chip (SoC). The method comprises generating a plurality of verification specific abstracted views of the IP core each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view of the IP-core is generated. |
申请公布号 |
US8533647(B1) |
申请公布日期 |
2013.09.10 |
申请号 |
US201213645897 |
申请日期 |
2012.10.05 |
申请人 |
ATRENTA, INC. |
发明人 |
GANGADHARAN SRIDHAR;MOVAHED-EZAZI MOHAMMAD H.;SARWARY SHAKER;MAAMARI FADI;RAY SUBIR SUBIR |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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