发明名称 Phase locked loop with digital compensation for analog integration
摘要 A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.
申请公布号 US8531219(B1) 申请公布日期 2013.09.10
申请号 US201313866871 申请日期 2013.04.19
申请人 QUALCOMM INCORPORATED 发明人 DUNWORTH JEREMY D.;BALLANTYNE GARY J.;ASURI BHUSHAN S.;GENG JIFENG;SAHOTA GURKANWAL S.
分类号 H03L7/06 主分类号 H03L7/06
代理机构 代理人
主权项
地址