发明名称 Interconnect barrier structure and method
摘要 A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device.
申请公布号 US8531035(B2) 申请公布日期 2013.09.10
申请号 US201113222639 申请日期 2011.08.31
申请人 YU CHEN-HUA;CHIOU WEN-CHIH;WU TSANG-JIUH;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 YU CHEN-HUA;CHIOU WEN-CHIH;WU TSANG-JIUH
分类号 H01L23/52;H01L21/44;H01L21/4763;H01L23/48;H01L29/40 主分类号 H01L23/52
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