发明名称 |
INTEGRATED CIRCUIT HAVING DATA RETENTION CIRCUITRY WITH LOW LEAKAGE AND METHOD THEREOF |
摘要 |
PROBLEM TO BE SOLVED: To provide a system and method for data retention circuitry with low leakage.SOLUTION: An integrated circuit comprises: a first circuit; and a sleep transistor circuit. The first circuit receives input signals and processes the input signals. The first circuit also retains data in a sleep state that has low leakage. The sleep transistor circuit is coupled to the first circuit and receives a sleep signal that has a negative voltage. The sleep circuit reduces power consumption of the first circuit in the sleep state to have low leakage on the basis of the sleep signal while retaining the data in the first circuit. |
申请公布号 |
JP2013179660(A) |
申请公布日期 |
2013.09.09 |
申请号 |
JP20130095072 |
申请日期 |
2013.04.30 |
申请人 |
MOSAID TECHNOLOGIES INC |
发明人 |
BARRY HOBERMAN;DANIEL HILLMAN;WILLIAM WALKER;CHARAHAN JOHN;MICHAEL ZAMPAGLIONE;COLE ANDREW |
分类号 |
H03K3/037;H03K3/356;H03K3/3562;H03K17/10 |
主分类号 |
H03K3/037 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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