发明名称 |
DISPOSITIF DE MEMOIRE DU TYPE ELECTRIQUEMENT PROGRAMMABLE ET EFFACABLE, A DEUX CELLULES PAR BIT |
摘要 |
<p>The device has a non volatile electrically programmable and erasable memory point (PTM) comprising memory cells (CEL1, CEL2) respectively connected to bit lines using two bit line selection transistors. A common terminal (S1) between the bit line selection transistor (TSBL1) and a floating gate transistor (TGF1) of one memory cell is connected to a control gate (CG2) of another floating gate transistor (TGF2) of another memory cell.</p> |
申请公布号 |
FR2952227(B1) |
申请公布日期 |
2013.09.06 |
申请号 |
FR20090057623 |
申请日期 |
2009.10.29 |
申请人 |
STMICROELECTRONICS (ROUSSET) SAS |
发明人 |
TAILLIET FRANCOIS |
分类号 |
H01L27/115;G11C16/10;G11C16/14 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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