| 摘要 |
The present invention relates to a processor core having an execution unit comprising an arrangement of Arithmetic-Logic- Units, wherein the operation mode of the execution unit is switchable between an asynchronous operation of the Arithmetic-Logic-Units and interconnection between the Arithmetic-Logic-Units such that a signal.from the register file crosses the execution unit and is receipt by the register file in one clock cycle; and wherein a pipelined operation mode of at least one of the Arithmetic-Logic-Units and the interconnection between the Arithmetic-Logic-Units such that a signal requires from the register file through the execution unit back to the register file more than one clock cycles. |
