MEMORY DEVICE LATCHING SYSTEM

摘要

A memory device latching system includes a processor. A plurality of memory devices are coupled to the processor through respective memory sockets. A first memory socket includes a first latch member having a first latch actuation member and defining a second latch member channel. A second memory socket includes a second latch member having a second latch actuation member and defining a first latch member channel. The first memory socket and the second memory socket are mounted to a circuit board such that the first latch end is located adjacent the second latch end, and the first latch member and the second latch member are operable to move to open positions such that at least a portion of the first latch actuation member is located in the first latch member channel and at least a portion of the second latch actuation member is located in the second latch member channel.