发明名称 MEMORY ARCHITECTURE WITH CURRENT CONTROLLER AND REDUCED POWER CONSUMPTION
摘要 PROBLEM TO BE SOLVED: To provide techniques for resolving a problem of noise sensitivity and reducing power consumption in reading a voltage stored on a random access memory bit cell.SOLUTION: A memory architecture comprises at least one memory bit cell, and at least one read bit line whose voltage is controlled and changed by a current in a transistor inside the at least one memory bit cell. Each of the at least one memory bit cell is electrically connected to one of the at least one read bit line. The current in the transistor is stopped by an indicator. The indicator responds to an indication that the voltage on the at least one read bit line is greater than a predetermined threshold.
申请公布号 JP2013175275(A) 申请公布日期 2013.09.05
申请号 JP20130077994 申请日期 2013.04.03
申请人 JOHN LYNCH 发明人 JOHN LYNCH
分类号 G11C11/4091;G11C11/405 主分类号 G11C11/4091
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