发明名称 INFORMATION PROCESSOR AND FAILURE ANALYSIS METHOD IN THE INFORMATION PROCESSOR, AND COMPUTER PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide information related to a fault that is fatal in an electronic apparatus without reducing processing efficiency of a memory access instruction, when the fatal fault is generated and even when a CPU is executing an instruction that has no relation (asynchronization) with the fault.SOLUTION: An instruction execution unit 103 executes an access preparation instruction 108 storing a first physical address, generates a second address so that a first address read out from a program counter has the same address as an address in which an access instruction 110 is stored, generates a second physical address on the basis of the first physical address and the second address, executes a plurality of instructions 109 for replacing the first physical address stored in a resister 102 with the second physical address by storing the second physical address in the register, and executes the access instruction. The second control unit 106 notifies the outside of the second physical address when an accessed address has a fault.
申请公布号 JP2013175077(A) 申请公布日期 2013.09.05
申请号 JP20120039617 申请日期 2012.02.27
申请人 NEC CORP 发明人 UEDA KIYOSHI
分类号 G06F11/30 主分类号 G06F11/30
代理机构 代理人
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