发明名称 All digital phase locked loop and method of controlling the same
摘要 <p>There are provided an all digital phase locked loop and a method of controlling the same. The all digital phase locked loop includes a phase comparator comparing phases of a target signal having a reference frequency and a digital oscillation feedback signal having a feedback frequency; a virtual value controller controlling a preset initial virtual value according to a phase comparison result from the phase comparator to generate an adjusted virtual value when the reference frequency is a frequency included between two preset lower and higher digital codes; a random number generator generating a random number within a range of a plurality of virtual values; a comparator generating digital codes; and a digitally controlled oscillator generating an oscillation signal according to the digital codes from the comparator.</p>
申请公布号 EP2632049(A3) 申请公布日期 2013.09.04
申请号 EP20120275104 申请日期 2012.07.11
申请人 SAMSUNG ELECTRO-MECHANICS CO., LTD 发明人 KIM, YOO HWAN;NA, YOO SAM
分类号 H03L7/18;H03L7/085 主分类号 H03L7/18
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