发明名称 |
PLL DUAL EDGE LOCK DETECTOR |
摘要 |
A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal. |
申请公布号 |
EP2633620(A2) |
申请公布日期 |
2013.09.04 |
申请号 |
EP20110836846 |
申请日期 |
2011.10.13 |
申请人 |
MARVELL WORLD TRADE LTD. |
发明人 |
WANG, XIAOYUE;JAMAL, SHAFIQ M. |
分类号 |
H03D13/00;H03L7/095;H03L7/199 |
主分类号 |
H03D13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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