发明名称 Layout technique for stress management cells
摘要 An integrated circuit device layout is created based on charge carrier mobility characteristics of the device's non-functional cells. The charge carrier mobility of the non-functional cells can alter behavioral characteristics such as the hold time, setup time, or leakage current of nearby functional logic cells. Accordingly, a layout tool creates the layout for the integrated circuit device by selecting and placing non-functional cells having different mobility so as to selectively alter the characteristics of nearby logic cells.
申请公布号 US8527933(B2) 申请公布日期 2013.09.03
申请号 US201113237365 申请日期 2011.09.20
申请人 SHARMA PUNEET;FREESCALE SEMICONDUCTOR, INC. 发明人 SHARMA PUNEET
分类号 G06F17/50;G06F9/455 主分类号 G06F17/50
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