发明名称 Partial write on a low power memory architecture
摘要 A memory includes memory cells, data lines, block select lines, and selection circuitry. The data lines provide data to and from the memory cells and may be grouped into blocks. Each block includes data lines. Each of the block select lines is associated with a respective one of the blocks. The selection circuitry is select a block in response to a respective block select line and the memory performs a memory operation using the selected bit line block.
申请公布号 US8526264(B2) 申请公布日期 2013.09.03
申请号 US201113172592 申请日期 2011.06.29
申请人 PARASHAR ANUJ;VERNET MARC;STMICROELECTRONICS INTERNATIONAL N.V. 发明人 PARASHAR ANUJ;VERNET MARC
分类号 G11C8/00 主分类号 G11C8/00
代理机构 代理人
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