发明名称 Digital to analog converter for phase locked loop
摘要 A digital to analog converter (DAC) that reduces sub-threshold leakage current in PLLs includes three series connected transistors, a unity gain buffer, and a switch. The system is connected between the voltage-to-current converter and a current-controlled oscillator. The DAC receives and accurately mirrors a current signal generated by a voltage-to-current converter.
申请公布号 US8525598(B2) 申请公布日期 2013.09.03
申请号 US201213351232 申请日期 2012.01.17
申请人 SAINI PRAVESH KUMAR;FREESCALE SEMICONDUCTOR, INC. 发明人 SAINI PRAVESH KUMAR
分类号 H03L7/00 主分类号 H03L7/00
代理机构 代理人
主权项
地址