| 摘要 |
A method of protecting a power supply voltage in an integrated circuit is disclosed. The method includes storing charge in a charge reservoir capacitor (142), receiving a power supply sample voltage (140), and receiving a load power supply voltage (VDDL, 102). The power supply sample voltage is compared to the load power supply voltage (150). Charge is added from the charge reservoir capacitor (142) to the load power supply (VDDL) through transistor 126 and capacitor 144 in response to the step of comparing.
|
