发明名称 LOCK DETECTION CIRCUIT, DLL CIRCUIT AND RECEPTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a lock detection circuit, a delay-locked loop circuit and a reception circuit which operate stably even in an initial state.SOLUTION: In an embodiment, the lock detection circuit includes an initial state response circuit for, when a pulse width modulation signal is not input, stopping a charge pump from outputting a second control signal, and outputting to delay lines a third control signal to control a delay amount of an entire delay circuit such that the delay amount is included in any one of a range where an OVER signal generation circuit is operable, a range where an UNDER signal generation circuit is operable, and a range higher than an UNDER threshold and lower than an OVER threshold.
申请公布号 JP2013172344(A) 申请公布日期 2013.09.02
申请号 JP20120035550 申请日期 2012.02.21
申请人 TOSHIBA CORP 发明人 UO TOYOAKI
分类号 H03L7/095;H03K5/13;H03K5/26;H03L7/081;H03L7/10;H04L7/02 主分类号 H03L7/095
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