发明名称 |
SIMD ACCELERATOR FOR DATA COMPARISON |
摘要 |
Some example embodiments include an apparatus for comparing a first operand to a second operand. The apparatus includes a SIMD accelerator configured to compare first multiple parts (e.g., bytes) of first operand to second multiple parts (e.g., bytes) of the second operand. The SIMD accelerator includes a ones' complement subtraction logic and a twos' complement logic configured to perform logic operations on the multiple parts of the first operand and the multiple parts of the second operand to generate a group of carry out and propagate data across bits of the multiple parts. At least a portion of the group of carry out and propagate data is reused in the group of logic operations.
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申请公布号 |
US2013227250(A1) |
申请公布日期 |
2013.08.29 |
申请号 |
US201213405021 |
申请日期 |
2012.02.24 |
申请人 |
HALLER WILHELM;KRAUCH ULRICH;LIND KURT;SCHROEDER FRIEDRICH;WOERNER ALEXANDER;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HALLER WILHELM;KRAUCH ULRICH;LIND KURT;SCHROEDER FRIEDRICH;WOERNER ALEXANDER |
分类号 |
G06F9/30;G06F9/302;G06F9/345 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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