发明名称 |
Layout design for a high power, gan-based fet |
摘要 |
<p>A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect (140) is disposed over the buffer layer and has a first end electrically connected to the source electrode (50). A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa. A gate pad (120) is disposed on the first dielectric layer adjacent the mesa. A conductive gate connect strip (110) is located over the gate node and is in contact therewith. The gate strip is in electrical contact with the gate pad. A source via is formed in the first dielectric layer and a source pad (150) is formed in the source via. The conductive source interconnect has a second end in electrical contact with the source pad.</p> |
申请公布号 |
EP2400553(A3) |
申请公布日期 |
2013.08.28 |
申请号 |
EP20110170153 |
申请日期 |
2011.06.16 |
申请人 |
POWER INTEGRATIONS, INC. |
发明人 |
LIU, LINLIN;POPHRISTIC, MILAN;PERES, BORIS |
分类号 |
H01L29/778;H01L29/06;H01L29/20;H01L29/417;H01L29/423 |
主分类号 |
H01L29/778 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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