| 摘要 |
A package for a microelectronic element 48, such as a semiconductor chip, has a dielectric mass 86 overlying the package substrate 56 and microelectronic element 48 and has top terminals 38 exposed at the top surface 94 of the dielectric mass 86. Traces 36a, 36b extending along edge surfaces 96, 108 of the dielectric mass 86 desirably connect the top terminals 38 to bottom terminals 64 on the package substrate 56. The dielectric mass 86 can be formed, for example, by molding or by application of a conformal layer 505. |
