发明名称 |
METHOD OF MAKING A MULTI-CHIP MODULE HAVING A REDUCED THICKNESS AND RELATED DEVICES |
摘要 |
A method of making a multi-chip module may include forming an interconnect layer stack on a sacrificial substrate. The interconnect layer stack may include patterned electrical conductor layers and a dielectric layer between adjacent patterned electrical conductor layers. The method may further include electrically coupling a first integrated circuit (IC) die in a flip chip arrangement to an uppermost patterned electrical conductor layer, and forming a first underfill dielectric layer between the first IC die and adjacent portions of the interconnect layer stack. The method further may include removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at a second integrated circuit die in a flip chip arrangement to the lowermost patterned electrical conductor layer. Still further, the method may include forming a second underfill dielectric layer between the second IC die and adjacent portions of the interconnect layer stack. |
申请公布号 |
EP2630656(A1) |
申请公布日期 |
2013.08.28 |
申请号 |
EP20110769973 |
申请日期 |
2011.09.21 |
申请人 |
HARRIS CORPORATION |
发明人 |
REED, THOMAS;HERNDON, DAVID;NICOL, DAVID;WEATHERSPOON, MICHAEL |
分类号 |
H01L21/98;H01L21/48;H01L21/56;H01L21/683;H01L25/065;H05K3/46 |
主分类号 |
H01L21/98 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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