| 摘要 |
<p>A system for dynamic power management in a distributed architecture system on chip, comprising a means for dynamically defining the feasibility of entering a low power mode of operation based on the status of components of the system, a means for entering or exiting safely from a low power state based on said feasibility, a means for decreasing the power centric communication between various processors and a means for increasing the low power mode time. Thus a framework is proposed in the instant invention wherein all the device drivers dynamically maintain the information on the feasibility of a low power transition at any point of time. Thus whenever an opportunity to enter a low power mode comes up one has to just check this feasibility variable to determine whether the low power mode entry is viable or not. For ensuring the safe transition to a low power mode, a stalling machine is proposed in case of DSPs. For further saving power, a power centric communication channel is established between various processors and to reduce the load on this communication channel techniques like quad-ring buffer and DSP feedback are proposed.</p> |
