发明名称 |
Structure, structure and method of latch-up immunity for high and low voltage integrated circuits |
摘要 |
Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.
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申请公布号 |
US8519402(B2) |
申请公布日期 |
2013.08.27 |
申请号 |
US20080183462 |
申请日期 |
2008.07.31 |
申请人 |
VOLDMAN STEVEN H.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
VOLDMAN STEVEN H. |
分类号 |
H01L27/108 |
主分类号 |
H01L27/108 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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