| 摘要 |
An address resolution device comprises flip-flops and adder, wherein outputs of each flip-flop are connected to corresponding inputs of adder which output is a device address output. Additionally it comprises decoder with cumulative sum, AND gates and device address input, wherein number of AND gates equals to number of flip-flops, and ADD gate is arranged in circuit between flip-flop output and its input to adder. First device address input is connected to inputs of decoder and adder, output of each flip-flop is connected to first input of AND gate, i-th output of decoder is connected to second input of i-th AND gate which first input is connected to output of i-th flip-flop, and outputs of AND gates are connected to corresponding inputs of adder as terminal point of flip-flop output–adder input circuit. |
