发明名称 Recessed contact for multi-gate FET optimizing series resistance
摘要 A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h1); forming a gate structure over the substrate, the gate structure having a length, a width and a height, the gate structure being perpendicular to the channel structure and being formed over the channel structure such that the channel structure passes through the width of the gate structure, where the height of the gate structure is greater than h1; reducing the height of the channel structure external to the gate structure so as to have a second height (h2); and depositing a silicide layer at least partially over the at least one channel structure external to the gate structure.
申请公布号 US8518770(B2) 申请公布日期 2013.08.27
申请号 US201213628169 申请日期 2012.09.27
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 LIN CHUNG-HSUN;CHANG JOSEPHINE B.
分类号 H01L21/8238 主分类号 H01L21/8238
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