发明名称 |
Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation |
摘要 |
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element. |
申请公布号 |
US8521994(B2) |
申请公布日期 |
2013.08.27 |
申请号 |
US20100975807 |
申请日期 |
2010.12.22 |
申请人 |
PELEG ALEXANDER;YAARI YAAKOV;MITTAL MILLIND;MENNEMEIER LARRY M.;EITAN BENNY;INTEL CORPORATION |
发明人 |
PELEG ALEXANDER;YAARI YAAKOV;MITTAL MILLIND;MENNEMEIER LARRY M.;EITAN BENNY |
分类号 |
G06F9/315;G06F9/30;G06F9/302;G06F9/318 |
主分类号 |
G06F9/315 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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