发明名称 |
INVALID WRITE PREVENTION FOR STT-MRAM ARRAY |
摘要 |
In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.
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申请公布号 |
US2013215675(A1) |
申请公布日期 |
2013.08.22 |
申请号 |
US201313853146 |
申请日期 |
2013.03.29 |
申请人 |
QUALCOMM INCORPORATED;QUALCOMM INCORPORATED |
发明人 |
RYU KYUNGHO;KIM JISU;JUNG SEONG-OOK;KANG SEUNG H. |
分类号 |
G11C11/16;H01L43/12 |
主分类号 |
G11C11/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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