发明名称 LSI DESIGN METHOD
摘要 Buffers on a clock tree are reduced, as long as there is enough set-up margin, in order to reduce power consumption in the clock tree. An FF group coupled to a partial tree, which is a part of the clock tree and expanded from the branch point being focused on, is defined as the target FF and the other FFs are defined as non-target FFs. The target buffer of an elimination candidate and the target and non-target FFs are defined so as not to change the slack in principle in a signal propagation path between the non-target FFs even if the buffer is eliminated. The buffer which can be eliminated is specified within a range in each signal propagation path which has a start point at the non-target FF and an end point at the target FF and in each signal propagation path between the target FFs.
申请公布号 US2013219352(A1) 申请公布日期 2013.08.22
申请号 US201313769885 申请日期 2013.02.19
申请人 RENESAS ELECTRONICS CORPORATION;RENESAS ELECTRONICS CORPORATION 发明人 ISHIKAWA RYOJI;KOBAYAKAWA OSAMU
分类号 G06F17/50 主分类号 G06F17/50
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