| 摘要 |
Provided is an integral A/D converter in which power consumption can be kept down while the conversion accuracy and conversion speed are improved. This integral A/D conversion circuit (1) is provided with: a comparator (10) for comparing the input voltage and the reference voltage of a ramp waveform, and outputting a comparison signal; a DLL (50) for generating a plurality of clock signals including a main clock signal and a clock signal having a different phase; a delay adjustment circuit (20) for delaying the comparison signal by a length equal to or greater than one cycle of the main clock signal; a counter (30) for calculating the time from the start of ramp waveform change to inversion of the output of the comparator on the basis of the output signal from the delay adjustment circuit (20) and the main clock signal, and outputting the time as a high-order bit; and a TDC (40) for latching, decoding, and outputting as a low-order bit the plurality of clock signals generated by the DLL (50) when the output of the delay adjustment circuit (20) is inverted; the TDC (40) starting operation by inversion of the comparison signal, and to stopping operation by inversion of the output signal from the delay adjustment circuit (20). |
