发明名称 SCHEDULING IN A MULTICORE ARCHITECTURE
摘要 <p>PURPOSE: Scheduling in a multi core architecture is provided to improve runtime performance of an application, by allocating transactions or threads, which are able to execute scheduling, to processing resources more efficiently. CONSTITUTION: A multi-core processor includes a number of processor elements. At least a part of the processors are arranged in a pool of processor elements. Each processor element in the pool of the processor elements includes a first power saving mode and a second power saving mode saving more energy than the first power saving mode. A scheduler of multi core systems provides work packets to an optimum resource at optimum time according to the set of predefined rules. [Reference numerals] (AA) Generating; (BB) Preparing; (CC) Being satisfied; (DD) Blocking; (EE) Restoring; (FF) Being preempted; (GG) Being scheduled; (HH) Waiting resource/timeout; (II,KK) Stopping; (JJ) Performing; (LL) Completing/canceling; (MM) End</p>
申请公布号 KR20130093571(A) 申请公布日期 2013.08.22
申请号 KR20130067351 申请日期 2013.06.12
申请人 SYNOPSYS, INC.;FUJITSU SEMICONDUCTOR LIMITED 发明人 LIPPETT MARK DAVID
分类号 G06F9/38;G06F1/32;G06F9/46 主分类号 G06F9/38
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