| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock generation circuit that can keep generating a desired clock even if a reference clock is interrupted without requiring an original phase-locked loop to be modified.SOLUTION: A clock generation circuit 1 includes: a PLL circuit 10 at least partly comprising an analog circuit to output a clock CK1 synchronized with a reference clock CK0; an input interruption detection circuit 21 for detecting an interrupted state of the reference clock CK0; and an ADPLL circuit 23 for, if the input interruption detection circuit 21 detects an interrupted state of the reference clock CK0, generating a clock CK2 to be output in place of the clock CK1 on the basis of the reference clock CK0 just before the interruption of the reference clock CK0. |
