发明名称 Method and Apparatus for Ensuring Data Cache Coherency
摘要 A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality.
申请公布号 US2013219145(A1) 申请公布日期 2013.08.22
申请号 US201213555894 申请日期 2012.07.23
申请人 ISHERWOOD ROBERT GRAHAM;KO YIN NAM;IMAGINATION TECHNOLOGIES, LTD. 发明人 ISHERWOOD ROBERT GRAHAM;KO YIN NAM
分类号 G06F12/08 主分类号 G06F12/08
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