LOW EXTERNAL RESISTANCE ETSOI TRANSISTORS

摘要

A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.